The present invention relates to DRAM memories. More particularly the invention relates to a high packing density folded bitline DRAM memory array architecture.
Aggressive development in dynamic random access memory (DRAM) fabrication processes and the small DRAM cell size makes commodity DRAM the highest density memory today. The high density of DRAM makes it very attractive for portable electronic devices that require large amounts of memory, but in a relatively small package. A further development is full integration of electronic components onto a single silicon chip. Examples of this include application specific integrated circuits (ASIC) that pack logic functions, DSP""s, microcontrollers and memory onto a single semiconductor chip. In most ASIC applications, memory tends to occupy a relatively large percentage of area, therefore it is desirable to minimize the amount of area occupied by the integrated memory.
It is well known to practitioners in the art that a single DRAM memory cell typically includes an n-channel or p-channel access transistor connected in series to a storage capacitor. The storage capacitor can be of the stacked, trench or planar type. Of the three types, a DRAM using planar type storage capacitors is the least expensive to manufacture, whereas the stacked and trench capacitor processes require additional complex steps over planar storage capacitor DRAM processes. Although stacked and trench capacitor DRAM""s are found in commodity DRAM devices, they are less prevalent in highly integrated chips such as ASICs. This is because current manufacturing processes optimized for trench and stacked capacitor DRAM memory are not optimized for logic circuits. Similarly, manufacturing processes optimized for logic are not optimized for DRAM memory. Therefore, devices manufactured with one optimized process will either have memory or logic circuits operating at sub-standard performance levels. Although hybrid DRAM/logic processes have been developed, they are still relatively expensive and do not allow the memory and logic circuits to perform at their full potential.
Since planar capacitor DRAM processes are very similar to standard logic manufacturing processes, ASIC devices integrating logic with planar capacitor DRAM benefit from less expensive manufacturing costs and high performance from both logic circuits and memory. However, the reduced manufacturing cost for planar capacitor type dynamic memory is offset by the relatively poor packing density of its cells, resulting in DRAM arrays of lower density than memory arrays employing stacked or trench capacitors for the same area. Trench and stacked capacitor cells have storage capacitors built vertically relative to the semiconductor substrate to reduce the surface area occupied by the cell. Planar capacitor cells on the other hand, require large amounts of semiconductor surface area because their capacitor plates are formed on the same plane as the substrate surface.
There are two widely used DRAM memory array layout architectures, called open bitline and folded bitline architectures. Examples of the folded bitline architecture are shown in FIGS. 1 and 2, and an example of the open bitline architecture is shown in FIG. 3. Both architectures illustrate the arrangement of bitline sense amplifiers (BLSA), bitlines, planar capacitor memory cells and wordlines (WL) with respect to each other.
The schematic of FIG. 1 illustrates the poor packing density of planar capacitor cells arranged in a folded bitline architecture. In this particular example four bitlines, ten wordlines labelled as WL to WL+9, and a corresponding number of memory cells are shown. The folded bitline architecture of FIG. 1 will now be described. Each BLSA 10 is connected to a pair of complementary bitlines 12 and 14, labelled as BLi, BLi* and BLi+1, BLi+1*, which extend in parallel from one side of BLSA 10. Planar capacitor cells 16 are connected to each of the bitlines 12 and 14 via a respective bitline contact 18. Bitlines 12 and 14 are typically formed of aluminum above the cells 16 and polysilicon wordlines 24. Each cell 16 includes a cell plate diffusion, or active area 20 and an access transistor active area 22. Polysilicon wordlines 24 run in a direction perpendicular to the bitline direction, and cross over access transistor diffusion areas 22 of any cell 16 in their path. The cells 16 connected to the same wordline are commonly referred to as a row of memory cells. It should be noted that only the diffusion areas of the cells 16 are shown to simplify the figure, however, those of skill in the art will understand that a thin oxide dielectric layer covers each cell plate active area 20, which is then covered by a polysilicon layer acting as a capacitor plate. Those of skill in the art will also understand that prior to the deposition of the polysilicon wordlines 24, transistor gate oxides are formed over the memory cell access transistor channel regions. Planar capacitor cell fabrication methods are well known in the art, and do not require further discussion. The cells 16 of each row are interleaved with an adjacent row of cells 16 to maximize the packing density of the cells along the bitline direction. However, passing wordlines that run between two back-to-back cells 16, as shown in areas 26, limit the extent to which the cells can be packed together. There is the added disadvantage that the wordlines are formed of polysilicon, which has relatively high resistivity when compared to metal. Titanium or tungsten silicided wordlines have been used to reduce the effective resistance of the polysilicon wordlines, however, they are still more resistive than aluminum interconnections. Therefore this higher resistivity slows memory access times.
A solution proposed in the prior art to increase memory cell packing density along the wordline direction for folded bitline architectures is shown in FIG. 2. The architecture is almost identical to the architecture shown in FIG. 1, except for the shape of the memory cells. In FIG. 2, each memory cell includes a rectangular shaped cell plate active area 21 and an access transistor active area 22. Polysilicon wordlines 24 run in a direction perpendicular to the bitline direction, and cross over access transistor diffusion areas of all cells in their path. It is noted that each pair of memory cells sharing the same bitline contact form a xe2x80x9cCxe2x80x9d shape. Complementary bitlines 12 and 14 are connected to each bitline sense amplifier 10, and each bitline makes contact to a plurality of cells. To save space, every alternate row of xe2x80x9cCxe2x80x9d shaped pair of memory cells has its pairs of memory cells rotated by 180 degrees. This way, the bitline contacts 18 in a column are offset with each other, allowing the complementary bitlines to be placed closer together. Unfortunately, this arrangement results in a poor cells/bitline ratio, and as with the architecture shown in FIG. 1, the long polysilicon wordlines slow the memory access time.
The schematic of FIG. 3 illustrates planar capacitor memory cells arranged in an open bitline architecture. All the elements shown in FIG. 3 are identical to those described in FIG. 1, except that they are arranged differently. More specifically, the complementary pair of bitlines 12 and 14 extend from opposite sides of BLSA 10. Now there are no passing wordlines, and a memory cell packing density higher than that for the folded bitline architecture shown in FIG. 1 is achieved. In addition, a polysilicon top cell plate 28 is shown overlayed upon the cell plate diffusion areas 20 of the cells connected to wordlines WL+5 and WL+6. Similar top cell plates are formed over all the cell plate diffusion areas 20, but not shown in FIG. 3 to simplify the schematic. However, unbalanced noise in a complementary pair of bitlines is a problem that is undesired because an activated wordline capacitively couples to all the bitlines it crosses, adding noise to those bitlines. For example, in the open bitline scheme of FIG. 3, wordline 24 only crosses bitline 12 while bitline 14 remains undisturbed. This inbalance can cause read errors by BLSA 10. This problem is not significant in the folded bitline architecture of FIG. 1 because the same wordline 24 crosses both bitlines 12 and 14, leaving both bitlines 12 and 14 balanced during wordline activation.
Another problem with the proximal arrangement of planar capacitor cells is potential capacitive coupling between adjacent back-to-back storage capacitors. In the example shown in FIG. 3, the back-to-back cell plate active areas 20 of memory cells along adjacent rows are typically covered by a common polysilicon cell plate that is connected to a cell plate potential. Although field oxide isolation is formed between each cell plate diffusion area 20, leakage can still occur due to the parasitic field oxide transistor that is formed between the adjacent cell plate diffusion areas 20. This leakage will cause stored charge do dissipate, resulting in reduced retention time, increased refresh rates and power consumption.
Additionally, as arrays become larger, bitlines become longer, adding undesired capacitance and slowing the operating speed. Polysilicon wordlines also become longer, adding more resistance to the wordlines.
Therefore, there is a need for a folded bitline memory architecture that allows for high memory cell packing density, and improved performance by reducing the wordline resistance and bitline capacitance.
It is an object of the present invention to obviate or mitigate at least one disadvantage of the prior art. In particular, it is an object of the present invention to provide folded bitline architecture having high memory cell packing density and reduced wordline and bitline resistance and capacitance.
In a first aspect, the present invention provides a folded bitline memory array. The folded bitline memory array has pairs of memory cells in a linear row, each pair of memory cells being coupled to a complementary folded bitline. Logically different wordline segments are coupled to each pair of memory cells, and metal wordlines are coupled to logically identical wordline segments.
In an embodiment of the present aspect, the pairs of memory cells in the linear row are adjacent to each other or interleaved with each other. The memory cells can be planar capacitor DRAM cells and the memory cells of two adjacent rows of memory cells share the same bitline contacts. In a further aspect of the present embodiment, rows of memory cells with back-to-back planar capacitors are offset with each other by a predetermined pitch, where the predetermined pitch can be up to one half of a memory cell pitch.
In yet another embodiment of the present aspect, each polysilicon wordline segment is coupled to two memory cells of the row of memory cells. In an alternative embodiment, each polysilicon wordline segment is coupled to four memory cells of the row of memory cells. In a further embodiment of the present aspect, each metal wordline is coupled to half of the memory cells of the row of memory cells and alternate polysilicon wordline segments of the row of memory cells are connected to the same metal wordline. The memory cells can be dual port planar capacitor DRAM cells in yet another embodiment of the present aspect.
In another aspect, the present invention provides a folded bitline memory array having a first memory cell linearly adjacent to a second memory cell, a folded bitline connected to the first memory cell, a complementary folded bitline connected to the second memory cell, a first wordline segment coupled to the first memory cell, and a second wordline segment coupled to the second memory cell where the first and second wordline segments are logically different wordlines.
In an embodiment of the present aspect, the first memory cell shares a bitline contact with a third memory cell linearly adjacent to a fourth memory cell, and the second memory cell shares a common bitline contact with the fourth memory cell. In a further aspect of the present embodiment, the first, second, third and fourth memory cells have planar storage capacitors, and two rows of linearly adjacent memory cells are offset with each other by a predetermined pitch.
In a further aspect, the present invention provides a folded bitline memory array having a first, second, third and fourth memory cell a first and second folded bitline, a first and second complementary folded bitline, and a first and second wordline segment. The first memory cell is linearly adjacent to a second memory cell. The third memory cell is linearly adjacent to the second memory cell and the fourth memory cell. The first folded bitline is connected to the first memory cell. The first complementary folded bitline is connected to the third memory cell. The second folded bitline is connected to the second memory cell. The second complementary folded bitline is connected to the fourth memory cell. The first wordline segment is coupled to the first and second memory cells. The second wordline segment is coupled to the third and fourth memory cells, and the first and second wordline segments are logically different wordlines
Other aspects and features of the present invention will become apparent to those ordinarily skilled in the art upon review of the following description of specific embodiments of the invention in conjunction with the accompanying figures.